add multi-ported memory link
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 4 Sep 2020 21:08:18 +0000 (22:08 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 4 Sep 2020 21:08:20 +0000 (22:08 +0100)
resources.mdwn

index 95f2c319f145fd410754ba4c0e3728ebcdcf409a..72a59f648ed80464a2200901c79e4648662f2370 100644 (file)
@@ -328,6 +328,8 @@ Some learning resources I found in the community:
 * Efabless "Openlane" <https://github.com/efabless/openlane>
 * Co-simulation plugin for verilator, transferring to ECP5
   <https://github.com/vmware/cascade>
+* Multi-read/write ported memories
+  <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
 
 
 # Real/Physical Projects