whoops fix change of variable (state) msr/pc

diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py
index b7ea7b4e37af009cb61b02373566fcd8ad7d246e..5ec59766361470d8617dc567ab5e48ef129ca3e9 100644 (file)
--- a/src/soc/fu/trap/test/test_pipe_caller.py
+++ b/src/soc/fu/trap/test/test_pipe_caller.py
@@ -224,8 +224,8 @@ class TestRunner(unittest.TestCase):
 
                     # ask the decoder to decode this binary data (endian'd)
                     yield pdecode2.dec.bigendian.eq(bigendian)  # little / big?
-                    yield pdecode2.msr.eq(msr)  # set MSR in pdecode2
-                    yield pdecode2.cia.eq(pc)  # set CIA in pdecode2
+                    yield pdecode2.state.msr.eq(msr)  # set MSR in pdecode2
+                    yield pdecode2.state.pc.eq(pc)  # set CIA in pdecode2
                     yield instruction.eq(ins)          # raw binary instr.
                     yield Settle()
                     fn_unit = yield pdecode2.e.do.fn_unit