test_issuer_mmu_data_path.py needs to use wb_get because of

reading from i-cache cannot be done without it

diff --git a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
index 69ba8a1badfe76e5d6f5791d8f689725e03f26d7..4742af0f2be31b6422142429bd5d40e7c2348091 100644 (file)
--- a/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
+++ b/src/soc/fu/mmu/test/test_issuer_mmu_data_path.py
@@ -14,11 +14,16 @@ class MMUTestCase(TestAccumulatorBase):
     # other instructions here -> must be load/store
 
     def case_mmu_dar(self):
-        lst = [ "mfspr 1, 19",     # DAR to reg 1
+        lst = [
+                 "mfspr 1, 720",     # DAR to reg 1
+                "addi 7, 0, 1",
+                "mtspr 19, 3",      # reg 3 to DAR
+                "mulli 7, 0, 1",
               ]
 
         initial_regs = [0] * 32
         initial_regs[1] = 0x2
+        initial_regs[3] = 0x5
 
         initial_sprs = {'DAR': 0x87654321,
                         }
@@ -52,10 +57,12 @@ class MMUTestCase(TestAccumulatorBase):
 
 
 if __name__ == "__main__":
+    mem = {}
     unittest.main(exit=False)
     suite = unittest.TestSuite()
     suite.addTest(TestRunner(MMUTestCase().test_data,
                              microwatt_mmu=True,
-                             svp64=False))
+                             svp64=False,
+                             rom=mem))
     runner = unittest.TextTestRunner()
     runner.run(suite)

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index afc245137b3ccf1bcfbe009c29f61a295cb0b1de..56978f763d762e7b862331cdc62b8575fde9ac20 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -242,7 +242,7 @@ class HDLRunner(StateRunner):
 
         # XXX for now, when ROM (run under wb_get) is detected,
         # skip setup of memories.  must be done a different way
-        if not self.dut.rom:
+        if self.dut.rom is None:
             yield from setup_i_memory(imem, pc, instructions, self.dut.rom)
             yield from setup_tst_memory(l0, self.test.mem)
         else: