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diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 4e5998ec2f172aef22a03a65c80938a2aa2183f4..141939691bc9aaa9998b21c1984d00655bf2d49c 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -28,7 +28,7 @@ Modes apply to Arithmetic and Logical SVP64 operations:
   *VL is altered as a result*.
 * **sat mode** or saturation: clamps each element result to a min/max rather than overflows / wraps.  allows signed and unsigned clamping for both INT
 and FP.
-* **reduce mode**. a mapreduce is performed.  the result is a scalar.  a result vector however is required, as the upper elements may be used to store intermediary computations.  the result of the mapreduce is in the first element with a nonzero predicate bit.  see [[appendix]]
+* **reduce mode**. a mapreduce is performed.  the result is a scalar.  a result vector however is required, as the upper elements may be used to store intermediary computations.  the result of the mapreduce is in the first element with a nonzero predicate bit.  see [[svp64/appendix]]
   note that there are comprehensive caveats when using this mode.
 * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the 
 *destination* predicate bit was zero.  When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed.  See appendix for details.