clarify C.MV VMERGE

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index 22310985c8bbebe971bd501fe3b722a0106ec287..30f147d61537a024c2916b5bf235fd65531e1740 100644 (file)
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -624,8 +624,8 @@ vector | vector  | src == dest   | sparse VCOPY   |
 """]]
 
 Also, VMERGE may be implemented as back-to-back (macro-op fused) C.MV
-operations with inversion on the src and dest predication for one of the
-two C.MV operations.
+operations with zeroing off, and inversion on the src and dest
+predication for one of the two C.MV operations.
 
 ### FMV, FNEG and FABS Instructions
 

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 84d5f5fca804b7d720c344c64e1aaef12ecf65ae..7d929c907b63be2f0ca07289170a537d9da8970d 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -1375,8 +1375,11 @@ vector | vector  | src == dest   | sparse VCOPY   |
 """]]
 
 Also, VMERGE may be implemented as back-to-back (macro-op fused) C.MV
-operations with inversion on the src and dest predication for one of the
-two C.MV operations.
+operations with zeroing off, and inversion on the src and dest predication
+for one of the two C.MV operations.  The non-inverted C.MV will place
+one set of registers into the destination, and the inverted one the other
+set.  With predicate-inversion, copying and inversion of the predicate mask
+need not be done as a separate (scalar) instruction.
 
 Note that in the instance where the Compressed Extension is not implemented,
 MV may be used, but that is a pseudo-operation mapping to addi rd, x0, rs.