add compressed decoder

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index de5fc334640d9df71d90246726ce16c7db872769..558cc0c92073915149d26d2521ff6efacefb90a7 100644 (file)
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -112,3 +112,4 @@ called the flip-flops orchestrating the timing "collectors".
 * Register File Bank Cacheing <https://www.princeton.edu/~rblee/ELE572Papers/MultiBankRegFile_ISCA2000.pdf>
 * Discussion <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2018-November/000157.html>
 * <https://github.com/UCSBarchlab/PyRTL/blob/master/examples/example5-instrospection.py>
+* <https://github.com/ataradov/riscv/blob/master/rtl/riscv_core.v#L210>