rs6000.c (rs6000_gimple_fold_builtin): Add handling for early expansion of vector...
authorWill Schmidt <will_schmidt@vnet.ibm.com>
Fri, 12 May 2017 15:40:04 +0000 (15:40 +0000)
committerWill Schmidt <willschm@gcc.gnu.org>
Fri, 12 May 2017 15:40:04 +0000 (15:40 +0000)
[gcc]

2017-05-10  Will Schmidt  <will_schmidt@vnet.ibm.com>

* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling for
early expansion of vector divide builtins.
(builtin_function_type): Add VSX_BUILTIN_UDIV_V2DI to the list of
builtins identified as having unsigned arguments.

[gcc/testsuite]

2017-05-10  Will Schmidt  <will_schmidt@vnet.ibm.com>

* gcc.target/powerpc/fold-vec-div-float.c: New.
* gcc.target/powerpc/fold-vec-div-floatdouble.c: New.
* gcc.target/powerpc/fold-vec-div-longlong.c: New.

From-SVN: r247977

gcc/ChangeLog
gcc/config/rs6000/rs6000.c
gcc/testsuite/ChangeLog
gcc/testsuite/gcc.target/powerpc/fold-vec-div-float.c [new file with mode: 0644]
gcc/testsuite/gcc.target/powerpc/fold-vec-div-floatdouble.c [new file with mode: 0644]
gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c [new file with mode: 0644]

index 852630e3ee46a40dce0728fa798d8f985f10782e..4339e570b6eb52fd1239797a4f3bbd2c5e459d2b 100644 (file)
@@ -1,4 +1,11 @@
-2017-05-10  Will Schmidt  <will_schmidt@vnet.ibm.com>
+2017-05-12  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+       * config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Add handling for
+       early expansion of vector divide builtins.
+       (builtin_function_type): Add VSX_BUILTIN_UDIV_V2DI to the list of
+       builtins identified as having unsigned arguments.
+
+2017-05-12  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
        * config/rs6000/rs6000.c (gimple-fold.h): New #include.
        (rs6000_gimple_fold_builtin): Add handling for early GIMPLE
index 2290439cfe3c1f03fe7c75901d1b1b7e5d178794..dac673ca53842385a2aa3a47c90fa3d120e1d33d 100644 (file)
@@ -17205,6 +17205,30 @@ rs6000_gimple_fold_builtin (gimple_stmt_iterator *gsi)
        gsi_replace (gsi, g, true);
        return true;
       }
+    /* Flavors of vec_div (Integer).  */
+    case VSX_BUILTIN_DIV_V2DI:
+    case VSX_BUILTIN_UDIV_V2DI:
+      {
+       arg0 = gimple_call_arg (stmt, 0);
+       arg1 = gimple_call_arg (stmt, 1);
+       lhs = gimple_call_lhs (stmt);
+       gimple *g = gimple_build_assign (lhs, TRUNC_DIV_EXPR, arg0, arg1);
+       gimple_set_location (g, gimple_location (stmt));
+       gsi_replace (gsi, g, true);
+       return true;
+      }
+    /* Flavors of vec_div (Float).  */
+    case VSX_BUILTIN_XVDIVSP:
+    case VSX_BUILTIN_XVDIVDP:
+      {
+       arg0 = gimple_call_arg (stmt, 0);
+       arg1 = gimple_call_arg (stmt, 1);
+       lhs = gimple_call_lhs (stmt);
+       gimple *g = gimple_build_assign (lhs, RDIV_EXPR, arg0, arg1);
+       gimple_set_location (g, gimple_location (stmt));
+       gsi_replace (gsi, g, true);
+       return true;
+      }
     /* Flavors of vec_and.  */
     case ALTIVEC_BUILTIN_VAND:
       {
@@ -18946,6 +18970,7 @@ builtin_function_type (machine_mode mode_ret, machine_mode mode_arg0,
     case MISC_BUILTIN_DIVWEUO:
     case MISC_BUILTIN_DIVDEU:
     case MISC_BUILTIN_DIVDEUO:
+    case VSX_BUILTIN_UDIV_V2DI:
       h.uns_p[0] = 1;
       h.uns_p[1] = 1;
       h.uns_p[2] = 1;
index 1bffa4a82ba1ed29e79c2d67b07296bcc698ce71..82cd82d52f05e8c202fb4fea8762d06197482497 100644 (file)
@@ -1,3 +1,9 @@
+2017-05-12  Will Schmidt  <will_schmidt@vnet.ibm.com>
+
+       * gcc.target/powerpc/fold-vec-div-float.c: New.
+       * gcc.target/powerpc/fold-vec-div-floatdouble.c: New.
+       * gcc.target/powerpc/fold-vec-div-longlong.c: New.
+
 2017-05-12  Will Schmidt  <will_schmidt@vnet.ibm.com>
 
        * gcc.target/powerpc/fold-vec-logical-ands-char.c: New.
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-float.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-float.c
new file mode 100644 (file)
index 0000000..8e8f645
--- /dev/null
@@ -0,0 +1,16 @@
+/* Verify that overloaded built-ins for vec_div with float
+   inputs produce the right results with -maltivec.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_altivec_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector float
+test1 (vector float x, vector float y)
+{
+  return vec_div (x, y);
+}
+
+/* { dg-final { scan-assembler-times {\mxvdivsp\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-floatdouble.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-floatdouble.c
new file mode 100644 (file)
index 0000000..0559013
--- /dev/null
@@ -0,0 +1,16 @@
+/* Verify that overloaded built-ins for vec_div with float and
+   double inputs for VSX produce the right results with -mvsx. */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-maltivec" } */
+
+#include <altivec.h>
+
+vector double
+test2 (vector double x, vector double y)
+{
+  return vec_div (x, y);
+}
+
+/* { dg-final { scan-assembler-times {\mxvdivdp\M} 1 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c
new file mode 100644 (file)
index 0000000..c37c648
--- /dev/null
@@ -0,0 +1,22 @@
+/* Verify that overloaded built-ins for vec_div with long long
+   inputs produce the right results.  */
+
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-maltivec -mpower8-vector -O3" } */
+
+#include <altivec.h>
+
+vector signed long long
+test3 (vector signed long long x, vector signed long long y)
+{
+  return vec_div (x, y);
+}
+
+vector unsigned long long
+test6 (vector unsigned long long x, vector unsigned long long y)
+{
+  return vec_div (x, y);
+}
+/* { dg-final { scan-assembler-times {\mdivd\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mdivdu\M} 2 } } */