[libre-riscv-dev] [Bug 195] Formal correctness framework is needed for Power ISA
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Thu, 21 May 2020 13:02:18 +0000 (13:02 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Thu, 21 May 2020 13:02:19 +0000 (14:02 +0100)
b4/9077508e61cc7e1336ced9293bf661a9273bfe [new file with mode: 0644]

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+Date: Thu, 21 May 2020 13:02:18 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: changed
+X-Bugzilla-Watch-Reason: None
+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Formal Verification
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
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+X-Bugzilla-Priority: ---
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+Message-ID: <bug-195-13-H7nur4ZwEs@https.bugs.libre-soc.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 195] Formal correctness framework is needed
+ for Power ISA
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