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mode bits name field correctly
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 15 Apr 2023 16:34:15 +0000 (17:34 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 15 Apr 2023 16:34:15 +0000 (17:34 +0100)
openpower/sv/rfc/ls009.mdwn patch | blob | history

diff --git a/openpower/sv/rfc/ls009.mdwn b/openpower/sv/rfc/ls009.mdwn
index be14b828ef5ffcaba8b3cf36acd22120c733a47a..886500e5115bb9a43d74d65251c4a1f95f67d9de 100644 (file)
--- a/openpower/sv/rfc/ls009.mdwn
+++ b/openpower/sv/rfc/ls009.mdwn
@@ -610,7 +610,7 @@ disabled: the register's elements are a linear (1D) vector.
 
 |31.30|29..28 |27..24| 23..21 | 20..18  | 17..12  |11..6 |5..0  | Mode  |
 |---- |------ |------| ------ | ------- | ------- |----- |----- | ----- |
-|0b00 |skip   |offset| invxyz | permute | zdimsz  |ydimsz|xdimsz|Matrix |
+|mode |skip   |offset| invxyz | permute | zdimsz  |ydimsz|xdimsz|Matrix |
 |0b00 |elwidth|offset|sk1/invxy|0b110/0b111|SVGPR|ydimsz|xdimsz|Indexed|
 |0b01 |submode|offset| invxyz | submode2| zdimsz  |mode  |xdimsz|DCT/FFT|
 |0b10 |submode|offset| invxyz | rsvd    | rsvd    |rsvd  |xdimsz|Preduce|
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