Merge pull request #210 from DurandA/master
authorTim Ansell <me@mith.ro>
Thu, 4 Jul 2019 00:23:36 +0000 (17:23 -0700)
committerGitHub <noreply@github.com>
Thu, 4 Jul 2019 00:23:36 +0000 (17:23 -0700)
Add verilog submodule from CPU cores to manifest


Trivial merge