get OP_FETCH_FAILED to respond/return an exception correctly

diff --git a/src/soc/fu/ldst/loadstore.py b/src/soc/fu/ldst/loadstore.py
index ad4d78f24f351854e29a8b26b6e39b54b5197b35..080d3320523914ac000cab1fb7014c1261bb3f16 100644 (file)
--- a/src/soc/fu/ldst/loadstore.py
+++ b/src/soc/fu/ldst/loadstore.py
@@ -292,6 +292,7 @@ class LoadStore1(PortInterfaceBase):
                     # TODO: critical that the write here has to
                     # notify the MMU FSM of the change to dsisr
                     comb += exception.eq(1)
+                    comb += self.done.eq(1)
                     sync += Display("MMU RADIX exception thrown")
                     sync += Display("TODO: notify MMU of change to dsisr")
                     sync += self.dsisr[63 - 33].eq(m_in.invalid)

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index 752f7ef60a53add90e971045166dfe58b2f62945..e1f2b2eed2c6c02e972621927ceb1a432682a943 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -227,9 +227,7 @@ class FSMMMUStage(ControlBase):
                     comb += ldst.priv_mode.eq(~msr_i[MSR.PR])
                     comb += ldst.maddr.eq(nia_i)
                     # XXX should not access this!
-                    mmu_done_delay = Signal()
-                    sync += mmu_done_delay.eq(mmu.d_in.done)
-                    comb += done.eq(mmu_done_delay)
+                    comb += done.eq(ldst.done)
                     comb += self.debug0.eq(3)
                     # LDST unit contains exception data, which (messily)
                     # is copied over, here.  not ideal but it will do for now