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diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 5b6b403e91898a4c978cc5e4b963eb00f60ef79b..9eeb514ffcc814c0fc7dc6318678b86eb84a7e38 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -23,7 +23,7 @@ Links:
 Simple-V is a type of Vectorisation best described as a "Prefix Loop
 Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR` instruction and to the 8086 `REP`
 Prefix instruction.  More advanced features are similar to the Z80
-`CPIR` instruction. If viewed as an actual Vector ISA it introduces
+`CPIR` instruction. If viewed one-dimensionally as an actual Vector ISA it introduces
 over 1.5 million 64-bit Vector instructions.  SVP64, the instruction
 format, is therefore best viewed as an orthogonal RISC-style "Prefixing"
 subsystem instead.