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diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn
index 54da2bae7fdf231df55879567d93b0ef81e74edc..9afc85daf0119d61af4ba89c96fb73b53f3976b1 100644 (file)
--- a/simple_v_extension/vblock_format.mdwn
+++ b/simple_v_extension/vblock_format.mdwn
@@ -168,9 +168,18 @@ The format is as follows:
 
 * status is the key field that effectively ezposes the inner FSM (Finite State Machine) directly.
 * status = 0b00 indicates that the processor is not in "VBLOCK Mode". It is instead in standard RV Scalar opcode execution mode. The processor will leave this mode only after it encounters the beginning of a valid VBLOCK opcode.
-* status=0b01 indicates that the VL Block has been read from the instruction stream and decoded (and copied into vlblk).
-* status=0b11 indicates that the Predicate and Register Blocks have been read from the instruction stream (and put into internal Vector Context)  Simpler implementations are permitted to reset status back to 0b10 and re-read the data after return from a trap. They are not however permitted to destroy opptr in the process.
 * status = 0b01 indicates that vlset, 16xil, pplen, rplen and mode have all been copied directly from the VBLOCK so that they do not need to be read again from the instruction stream.
+* status=0b10 indicates that the VL Block has been read from the instruction stream and decoded (and copied into vlblk).
+* status=0b11 indicates that the Predicate and Register Blocks have been read from the instruction stream (and put into internal Vector Context)  Simpler implementations are permitted to reset status back to 0b10 and re-read the data after return from a trap. They are not however permitted to destroy opptr in the process.
+* opptr points to where instructions begin in the VBLOCK. 0 indicates the start of the opcodes, and is in multiples of 16 bits ( 2 bytes).  This is the equivalent of a Program Counter, for VBLOCKs.
+
+When status=0b11, opptr may be written to using CSRRWI. Doing so will cause execution to jump within the block, exactly as if PC had been set in normal RISC-V eexecution. Writing a value outside of the range of the instruction block will cause an illegal instruction exception. Writing a value (any value) when status is not 0b11 likewise causes an illegal instruction exception.
+
+In privileged modes, obviously the above rules do not apply to the completely seoarate (x)ePCVBLK CSRs because these are copies of state, not the actual active PCVBLK. Writing to PCVBLK during a trap however, clearly the rules must apply.
+
+If PCVBLK is written to with CSRRW, the same rules apply, however the entire register is treated as the new opptr.
+
+Note that the value returned in the dest register is the *full* PCVBLK, not just the opptr part.
 
 # Limitations on instructions