HDL_workflow/ECP5_FPGA provide two images showing different orientation

of stlinkv2

diff --git a/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg b/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg
deleted file mode 100644 (file)
index c03ef96..0000000
Binary files a/HDL_workflow/jtag_wires_ulx3s_stlinkv2.jpg and /dev/null differ

diff --git a/HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg b/HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg
new file mode 100644 (file)
index 0000000..7d2687c
Binary files /dev/null and b/HDL_workflow/jtag_wires_ulx3s_stlinkv2_opposite_orientation_to_jtag.jpg differ

diff --git a/HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg b/HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg
new file mode 100644 (file)
index 0000000..6e5f8f6
Binary files /dev/null and b/HDL_workflow/jtag_wires_ulx3s_stlinkv2_same_orientation_as_jtag.jpg differ