wrong pspec variable in selecting pll clock

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 0d1fa1f22fc506ecf28dd2f29b698e57fd4b8d71..ae6c24bfde03546481aead6c04415b02a17a4554 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -453,7 +453,7 @@ class TestIssuer(Elaboratable):
         self.clksel = ClockSelect()
 
         # PLL direct clock or not
-        self.pll_en = hasattr(pspec, "use_pll") and pspec.pll_en
+        self.pll_en = hasattr(pspec, "use_pll") and pspec.use_pll
 
     def elaborate(self, platform):
         m = Module()