(no commit message)

diff --git a/3d_gpu/layouts/coriolis2_180nm.mdwn b/3d_gpu/layouts/coriolis2_180nm.mdwn
index 068af11b92dcb59735df1ee9498048d97169a6af..694303e415ab44aa01b74aa0135fba62a98bc64c 100644 (file)
--- a/3d_gpu/layouts/coriolis2_180nm.mdwn
+++ b/3d_gpu/layouts/coriolis2_180nm.mdwn
@@ -70,7 +70,16 @@ to ensure complete consistency across
 * IO Ring
 * JTAG Boundary Scan
 
-JTAG 
+JTAG also contains a Wishbone Master for direct access to Memory
+and also a DMI Interface for controlling the core.  In simulations
+a JTAG client was implemented both in nmigen HDL as well as
+verilator.  The exact same openocd scripts and direct
+JTAG connectivity using jtagremote can then be used on:
+
+* nmigen HDL simulations
+* verilator simulations
+* FPGA
+* ls180 ASIC
 
 [[!img 180nm_Oct2020/ls180.svg size="400x" ]]