(no commit message)
authorlkcl <lkcl@web>
Sun, 14 Nov 2021 18:20:28 +0000 (18:20 +0000)
committerIkiWiki <ikiwiki.info>
Sun, 14 Nov 2021 18:20:28 +0000 (18:20 +0000)
docs/pinmux.mdwn

index 1d340f226a67a165c335aba0941cb366b4ebf854..4dfde8ba4e12474d0fdf09db40f2c53ce0698ef3 100644 (file)
@@ -5,6 +5,7 @@ Links:
 * <http://www2.eng.cam.ac.uk/~dmh/4b7/resource/section14.htm>
 * <https://ftp.libre-soc.org/Pin_Control_Subsystem_Overview.pdf>
 * <https://bugs.libre-soc.org/show_bug.cgi?id=50>
+* <https://git.libre-soc.org/?p=c4m-jtag.git;a=tree;hb=HEAD>
 
 Managing IO on an ASIC is nowhere near as simple as on an FPGA.
 An FPGA has built-in IO Pads, the wires terminate inside an