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diff --git a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
index f6dde6311a930fbeb73ebf9b44df0fdd16362cc5..f2e7287e92b196726fe8ef5ead2a831b48d8690c 100644 (file)
--- a/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
+++ b/Comparative_analysis_Harmonised_RVP_vs_Andes_Packed_SIMD_ISA_proposal.mdwn
@@ -2,7 +2,7 @@
 
 Harmonised RVP is a proposal to provide SIMD functionality comparable to the Andes Packed SIMD ISA, but in a manner that is forwards compatible ("harmonised") with the RV Vector specification.
 
-An example use case is a string copy operation - using Harmonised RVP, binary code using SIMD instructions operating on integer registers to copy a string can also execute (unchanged) on a full RV Vector processor and use the dedicated vector unit to copy the string.  Harmonised RVP also upwards compatibility between RV32 and RV64 SIMD using this same approach.
+An example use case is a string copy operation - using Harmonised RVP, code can use integer register SIMD instructions to copy a string.  This code  can then also execute (unchanged) on a full RV Vector processor and use the dedicated vector unit to copy the string.  Harmonised RVP also upwards compatibility between RV32 and RV64 SIMD using this same approach.
 
 ## Register file comparison