use port name for INT regfile to match up with test_runner gtkw

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index fa8994613034a6338f15ed37f9d34e4b2487c09a..167ae5118a37d838227cace3b53da9b15f2e41fb 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -83,7 +83,7 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray):
             self.r_ports['rb'] = self.read_port("src2")
             self.r_ports['rc'] = self.read_port("src3")
         else:
-            self.r_ports['rabc'] = self.read_port("src")
+            self.r_ports['rabc'] = self.read_port("src1")
 
 
 # Fast SPRs Regfile

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index eb75d3b42977f9a7be17b6a7d02fead13b42c6ce..b6be2f3a20581a2482e9beb80490153bdd97230c 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -395,17 +395,18 @@ class TestRunner(FHDLTestCase):
             {'comment': 'instruction memory'},
             'imem.sram.rdport.memory(0)[63:0]',
             {'comment': 'registers'},
-            'core.int.rp_src.memory(0)[63:0]',
-            'core.int.rp_src.memory(1)[63:0]',
-            'core.int.rp_src.memory(2)[63:0]',
-            'core.int.rp_src.memory(3)[63:0]',
-            'core.int.rp_src.memory(4)[63:0]',
-            'core.int.rp_src.memory(5)[63:0]',
-            'core.int.rp_src.memory(6)[63:0]',
-            'core.int.rp_src.memory(7)[63:0]',
-            'core.int.rp_src.memory(9)[63:0]',
-            'core.int.rp_src.memory(10)[63:0]',
-            'core.int.rp_src.memory(13)[63:0]',
+            # match with soc.regfile.regfiles.IntRegs port names
+            'core.int.rp_src1.memory(0)[63:0]',
+            'core.int.rp_src1.memory(1)[63:0]',
+            'core.int.rp_src1.memory(2)[63:0]',
+            'core.int.rp_src1.memory(3)[63:0]',
+            'core.int.rp_src1.memory(4)[63:0]',
+            'core.int.rp_src1.memory(5)[63:0]',
+            'core.int.rp_src1.memory(6)[63:0]',
+            'core.int.rp_src1.memory(7)[63:0]',
+            'core.int.rp_src1.memory(9)[63:0]',
+            'core.int.rp_src1.memory(10)[63:0]',
+            'core.int.rp_src1.memory(13)[63:0]',
         ]
 
         if self.microwatt_mmu: