(no commit message)

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 750452b62a840348159d1d44a12b1ec8afe6a94e..180591001e8b74657e47321b3dd381923d6e1dfd 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -129,12 +129,13 @@ sequential element numbering are expressed or implied**
 Whilst the bits within the GPRs and FPRs are expected to be MSB0-ordered
 and for numbering to be sequentially incremental the element offset
 numbering is naturally **LSB0-sequentially-incrementing from zero not
-MSB0-incrementing.**  Expressed exclusively in MSB0-numbering, SVP64 is
+MSB0-incrementing.**  When exclusively using MSB0-numbering, SVP64
 becomes unnecessarily complex to both express and subsequently understand:
 the required subtractions from 63,
-31, 15 and 7 unfortunately become a hostile minefield.  Therefore for the
+31, 15 and 7 unfortunately become a hostile minefield, obscuring both
+intent and meaning. Therefore for the
 purposes of this section the more natural **LSB0 numbering is assumed**
-and it is up to the reader to translate to MSB0 numbering.
+and it is left to the reader to translate to MSB0 numbering.
 
 The Canonical specification for how element-sequential numbering and
 element-width overrides is defined is expressed in the following c