Limit outstanding range

outstanding can only ever be -1 to 2 at the moment (0 or 1 on a
rising clock edge). Vivado is synthesizing a much wider adder
which is silly. Constrain it with a range statement. This should
be good for timing and saves us about 85 LUTs.

This will get relaxed when we add more pipelining, but only by a
few bits.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/decode2.vhdl b/decode2.vhdl
index 44a130d345ce453e850ea336b9f7a63618303e40..8651b763cd53b6138e62d3e03ba165129a05b629 100644 (file)
--- a/decode2.vhdl
+++ b/decode2.vhdl
@@ -40,7 +40,7 @@ architecture behaviour of decode2 is
 
        type reg_internal_type is record
                state : state_type;
-               outstanding : integer;
+               outstanding : integer range -1 to 2;
        end record;
 
        type reg_type is record