(no commit message)

diff --git a/about_us.mdwn b/about_us.mdwn
index d36713bf42aa49273a273e379735e5a0dcf9ffb7..5db025edfa875169e54722062cba2fd7687a70ed 100644 (file)
--- a/about_us.mdwn
+++ b/about_us.mdwn
@@ -168,12 +168,6 @@ TODO, Adithya
 * Programming Languages: C, Python, Java, VHDL
 * Availability: ~8-10 hours/week
 
-### [[oa/Akshara S]]
-
-* Interests: Embedded systems, Analog Electronics
-* Programming Languages: C, Python, Verilog
-* Availability: ~ 3-4 hours/week
-
 ### [[oa/Sukhanshu D]]
 
 * Experience: SOC Verification Intern, Digital Design
@@ -185,11 +179,7 @@ TODO, Adithya
 * Interests: Digital Design, Verification, IC Fabrication
 * Programming Languages: Verilog, System Verilog, UVM
 * Availability: ~ 6-8 hours/week
-* Experience: SoC Verification Intern, Research Intern at KIST
-
-### [[oa/sparsha]]
-
-TODO
+* Experience: SoC Verification Intern, Research Intern at KIS
 
 ## 3mdeb