clarify section for regfiles

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 319ff875c866d28a3eb1f701cb764bc27ef652a3..6db9dcf5b6b5433abf3f9221b7217a125b7a498a 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -121,10 +121,12 @@ register-register operations.
 
 To be absolutely clear:
 
-**No conceptual arithmetic ordering or other changes over the Scalar Power ISA
-definitions to registers or register files
-or to arithmetic or Logical Operations beyond element-width subdivision and
-sequential element numbering are expressed or implied**
+```
+    No conceptual arithmetic ordering or other changes over the Scalar
+    Power ISA definitions to registers or register files or to arithmetic
+    or Logical Operations beyond element-width subdivision and sequential
+    element numbering are expressed or implied
+```
 
 Whilst the bits within the GPRs and FPRs are expected to be MSB0-ordered
 and for numbering to be sequentially incremental the element offset