add category descriptions

diff --git a/simple_v_extension/opcodes.mdwn b/simple_v_extension/opcodes.mdwn
index 478eeb7781a811f46609395c44be7193a1a6dcff..2241be0155aaef562d007e791f320b5c023b6158 100644 (file)
--- a/simple_v_extension/opcodes.mdwn
+++ b/simple_v_extension/opcodes.mdwn
@@ -18,7 +18,7 @@ indirectly adds on each RISC-V **standard** opcode.
   indirected) multi-register load operation where either or both of
   destination register or load-from-address register may be redirected,
   vectorised or **independently** predicated.
-* **vst**
+* **vst** - a matching multi-register store operation matching **vld**.
 * **VLU** - a "Unit Stride" variant of **vld** where instead of the
   source-address register number being (optionally) incremented
   (and redirected, and predicated) it is the **immediate offset**