config: Add a CPU clock command-line option
authorAkash Bagdia <akash.bagdia@arm.com>
Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)
committerAkash Bagdia <akash.bagdia@arm.com>
Thu, 27 Jun 2013 09:49:49 +0000 (05:49 -0400)
This patch adds a 'cpu_clock' command-line option and uses the value
to assign clocks to components running at the CPU speed (L1 and L2
including the L2-bus). The configuration scripts are updated
accordingly.

The 'clock' option is left unchanged in this patch as it is still used
by a number of components. In follow-on patches the latter will be
disambiguated further.

configs/common/CacheConfig.py
configs/common/Options.py
configs/example/fs.py
configs/example/ruby_fs.py
configs/example/se.py

index 5dd564f0cd3fad1f4f5075e1f3d53702dd9ec63b..288a633ce50d580512d6795c59e8290269bca5e4 100644 (file)
@@ -64,12 +64,12 @@ def config_cache(options, system):
         # are not connected using addTwoLevelCacheHierarchy. Use the
         # same clock as the CPUs, and set the L1-to-L2 bus width to 32
         # bytes (256 bits).
-        system.l2 = l2_cache_class(clock=options.clock,
+        system.l2 = l2_cache_class(clock=options.cpu_clock,
                                    size=options.l2_size,
                                    assoc=options.l2_assoc,
                                    block_size=options.cacheline_size)
 
-        system.tol2bus = CoherentBus(clock = options.clock, width = 32)
+        system.tol2bus = CoherentBus(clock = options.cpu_clock, width = 32)
         system.l2.cpu_side = system.tol2bus.master
         system.l2.mem_side = system.membus.slave
 
index f2bcbef0cd2b67caa660f59166c19ab571e5cb3a..08881cf11921bfd86c5579310b0cf1de0a020e04 100644 (file)
@@ -78,6 +78,9 @@ def addCommonOptions(parser):
     parser.add_option("--simpoint-interval", type="int", default=10000000,
                       help="SimPoint interval in num of instructions")
     parser.add_option("--clock", action="store", type="string", default='2GHz')
+    parser.add_option("--cpu-clock", action="store", type="string",
+                      default='2GHz',
+                      help="Clock for blocks running at CPU speed")
     parser.add_option("--num-dirs", type="int", default=1)
     parser.add_option("--num-l2caches", type="int", default=1)
     parser.add_option("--num-l3caches", type="int", default=1)
index b17266e54cbb89e5a96eb07c000d0faaa8114fa0..31106cba7e89eebe60e88f851fdf27b4061deb05 100644 (file)
@@ -81,8 +81,8 @@ def is_kvm_cpu(cpu_class):
 # system under test can be any CPU
 (TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
 
-TestCPUClass.clock = options.clock
-DriveCPUClass.clock = options.clock
+TestCPUClass.clock = options.cpu_clock
+DriveCPUClass.clock = options.cpu_clock
 
 # Match the memories with the CPUs, the driver system always simple,
 # and based on the options for the test system
index e04e14434b107c0162c076b4ce49c1000864bcb9..e6239caf4975bf6b9848753b6344f5e34fd36c30 100644 (file)
@@ -80,7 +80,7 @@ if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
     sys.exit(1)
 (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
 
-CPUClass.clock = options.clock
+CPUClass.clock = options.cpu_clock
 
 TestMemClass = Simulation.setMemClass(options)
 
index 299a2efb0535cecdad01d8ac02fb8e7835042b88..000390080066d98ee8e46dbae59c875d861fc17b 100644 (file)
@@ -147,7 +147,7 @@ else:
 
 
 (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
-CPUClass.clock = options.clock
+CPUClass.clock = options.cpu_clock
 CPUClass.numThreads = numThreads
 
 MemClass = Simulation.setMemClass(options)