add flexbus get/put link

diff --git a/src/bsv/bsv_lib/soc_template.bsv b/src/bsv/bsv_lib/soc_template.bsv
index e99b9b149839fd4d13e27e87b9b111b615ab5768..66cab5e32b2a3364ebde3941b85ae808fee287cf 100644 (file)
--- a/src/bsv/bsv_lib/soc_template.bsv
+++ b/src/bsv/bsv_lib/soc_template.bsv
@@ -213,6 +213,9 @@ package Soc;
                               vme.slave_axi_vme);
             `endif
 
+//          pin connections
+{9}
+
             // fabric connections
 {5}
 

diff --git a/src/bsv/peripheral_gen/flexbus.py b/src/bsv/peripheral_gen/flexbus.py
index 1de5141587c37fa4c7aa2b7447b9147d073fa294..8fed54702ac0e2cbfc1849950d7d8eb3735c26d7 100644 (file)
--- a/src/bsv/peripheral_gen/flexbus.py
+++ b/src/bsv/peripheral_gen/flexbus.py
@@ -24,20 +24,33 @@ class flexbus(PBase):
     def _mk_connection(self, name=None, count=0):
         return "fb{0}.axi_side"
 
+    def pinname_in(self, pname):
+        return {'ta': 'flexbus_side.tAn',
+               }.get(pname, '')
+
     def pinname_out(self, pname):
-        if pname in ['cmd', 'clk']:
-            return pname
-        return ''
+        return {'ale': 'flexbus_side.m_ALE',
+                'oe' : 'flexbus_side.m_OEn',
+                'rw' : 'flexbus_side.m_R_Wn',
+               }.get(pname, '')
 
     def mk_pincon(self, name, count):
         ret = [PBase.mk_pincon(self, name, count)]
         # special-case for gpio in, store in a temporary vector
         plen = len(self.peripheral.pinspecs)
-        template = "mkConnection({0}.{1},\n\t\t\t{2}.{1});"
+        template = "mkConnection({0}.{3},\n\t\t\t{2}.flexbus_side.{1});"
         sname = self.peripheral.iname().format(count)
         name = self.get_iname(count)
         ps = "pinmux.peripheral_side.%s" % sname
         n = "{0}".format(name)
-        for ptype in ['out', 'out_en', 'in']:
-            ret.append(template.format(ps, ptype, n))
+        for stype, ptype in [
+                ('cs', 'm_FBCSn'),
+                ('bwe', 'm_BWEn'),
+                ('tbst', 'm_TBSTn'),
+                ('tsiz', 'm_TSIZ'),
+                ('ad_in', 'm_AD'),
+                ('ad_out', 'm_din'),
+                ('ad_en', 'm_OE32n'),
+            ]:
+            ret.append(template.format(ps, ptype, n, stype))
         return '\n'.join(ret)

diff --git a/src/bsv/pinmux_generator.py b/src/bsv/pinmux_generator.py
index 03ee60911b8c912ea4c02fdfffdfcdaba738a438..12c281311664893e11fa7d459f74b5474d92bc98 100644 (file)
--- a/src/bsv/pinmux_generator.py
+++ b/src/bsv/pinmux_generator.py
@@ -155,6 +155,7 @@ def write_soc(soc, soct, p, ifaces, iocells):
         bsv_file.write(soct.format(imports, ifdecl, mkfast,
                                    slavedecl, mastdecl, mkcon,
                                    inst, dma, num_dmachannels,
+                                   pincon,
                                    ))
 
 

diff --git a/src/spec/i_class.py b/src/spec/i_class.py
index e1189898545367de88aa0064b164d02c4a9c3189..3e4b6783f4bc0da07672dcba0eb2f3768f9a0520 100644 (file)
--- a/src/spec/i_class.py
+++ b/src/spec/i_class.py
@@ -86,7 +86,7 @@ def pinspec():
 
     # see comment in spec.interfaces.PinGen, this is complicated.
     flexspec = {
-        'FB_TS': ('FB_ALE', 2),
+        #'FB_TS': ('FB_ALE', 2), # commented out for now
         'FB_CS2': ('FB_BWE2', 2),
         'FB_AD0': ('FB_BWE2', 3),
         'FB_CS3': ('FB_BWE3', 2),

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index 57611869913bfa989487e238a425182fc120858f..06c6504359181ff8d65af14ed7f1805bc9ea7a92 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -144,7 +144,8 @@ def flexbus1(suffix, bank):
     for i in range(2):
         buspins.append("CS%d+" % i)
     buspins += ['ALE+', 'OE+', 'RW+', 'TA-',
-                'TS+', 'TBST+',
+                # 'TS+',  commented out for now, mirrors ALE, for mux'd mode
+                'TBST+',
                 'TSIZ0+', 'TSIZ1+']
     for i in range(4):
         buspins.append("BWE%d+" % i)