add code-markers and appendix table to ls015

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index 68a8e930c2a9d2b00eba5633cc8cca4ed2201468..ed9474448668d2dcad71b445b27be4c1b5e1a58f 100644 (file)
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -101,6 +101,7 @@ OPF ISA WG):
 
 fmap is encoded in XO and is 4 bits
 
+```
     crrweird: RT,BFA,M,fmsk,fmap
 
     creg = CR{BFA}
@@ -113,6 +114,7 @@ fmap is encoded in XO and is 4 bits
     RT[63] = result # MSB0 numbering, 63 is LSB
     If Rc:
         CR0 = analyse(RT)
+```
 
 When used with SVP64 Prefixing this is a [[sv/normal]]
 SVP64 type operation and as such can use Rc=1 and RC1 Data-dependent
@@ -126,6 +128,7 @@ sequentially into the destination. *Destination elwidth overrides still apply*.
 
 fmap is encoded in XO and is 4 bits
 
+```
     mfcrrweird: RT,BFA,fmsk,fmap
 
     creg = CR{BFA}
@@ -137,6 +140,7 @@ fmap is encoded in XO and is 4 bits
     RT[60:63] = result # MSB0 numbering, 63 is LSB
     If Rc:
         CR0 = analyse(RT)
+```
 
 When used with SVP64 Prefixing this is a [[sv/normal]]
 SVP64 type operation and as such can use Rc=1 and RC1 Data-dependent
@@ -150,6 +154,7 @@ into the destination.  *Destination elwidth overrides still apply*
 
 fmap is encoded in XO and is 4 bits
 
+```
     mtcrrweird: BF,RA,M,fmsk,fmap
 
     a = (RA|0)
@@ -161,6 +166,7 @@ fmap is encoded in XO and is 4 bits
     if M:
         result |= CR{BF} & ~fmsk
     CR{BF} = result
+```
 
 When used with SVP64 Prefixing this is a [[sv/normal]]
 SVP64 type operation and as such can use RC1 Data-dependent
@@ -171,6 +177,7 @@ on the `BF` CR Field. When M=0 it is a more normal Write.
 
 **mtcrweird**
 
+```
     mtcrweird: BF,RA,M,fmsk,fmap
 
     reg = (RA|0)
@@ -183,6 +190,7 @@ on the `BF` CR Field. When M=0 it is a more normal Write.
     if M:
         result |= CR{BF} & ~fmsk
     CR{BF} = result
+```
 
 Note that when M=1 this operation is a Read-Modify-Write on the CR Field
 BF. Masked-out bits of the 4-bit CR Field BF will not be changed when
@@ -204,6 +212,7 @@ Unlike `mcrf` the bits of the CR Field may not change position:
 the EQ bit from the source may only go into the EQ bit of the
 destination (optionally inverted, set, or cleared).
 
+```
     mcrfm: BF,BFA,M,fmsk,fmap
 
     result = fmsk & CR{BFA}
@@ -211,6 +220,7 @@ destination (optionally inverted, set, or cleared).
         result |= CR{BF} & ~fmsk
     result ^= fmap
     CR{BF} = result
+```
 
 When M=1 this operation is a Read-Modify-Write on the CR Field
 BF. Masked-out bits of the 4-bit CR Field BF will not be changed when
@@ -230,6 +240,7 @@ individual bits in BF may be set to 1 by ensuring that the required bit of
 
 **crweirder**
 
+```
     crweirder: BT,BFA,fmsk,fmap
 
     creg = CR{BFA}
@@ -243,6 +254,7 @@ individual bits in BF may be set to 1 by ensuring that the required bit of
     bf = BT[2:4] # select CR field
     bit = BT[0:1] # select bit of CR field
     CR{bf}[bit] = result # aka the usual "CR[32+BT] = result"
+```
 
 When used with SVP64 Prefixing this is a [[sv/cr_ops]] SVP64
 type operation that has 5-bit Data-dependent and 5-bit Predicate-result
@@ -253,9 +265,11 @@ on the `BT` CR bit. When M=0 it is a more normal Write.
 
 **Example Pseudo-ops:**
 
+```
     mtcri BF, fmap    mtcrweird BF, r0, 0, 0b1111,~fmap
     mtcrset BF, fmsk  mtcrweird BF, r0, 1, fmsk,0b0000
     mtcrclr BF, fmsk  mtcrweird BF, r0, 1, fmsk,0b1111
+```
 
 ----------
 
@@ -284,6 +298,7 @@ operand) elwidth field still sets the Integer element size as usual
 
 **crrweird: RT, BB, fmsk.fmap**
 
+```
     for i in range(VL):
         if BB.isvec:
             creg = CR{BB+i}
@@ -318,6 +333,7 @@ operand) elwidth field still sets the Integer element size as usual
                 iregs[RT+i//8][63-(i%8)] = result
         else:
             iregs[RT][63-i] = result # results also in scalar INT
+```
 
 Note that:
 
@@ -355,6 +371,7 @@ result elements would like to be packed, but RT.elwidth determines
 the limit. Any parts of the destination elements not containing
 results are set to zero.
 
+```
     for i in range(VL):
         if BB.isvec:
             creg = CR{BB+i}
@@ -387,13 +404,16 @@ results are set to zero.
             # exceeding VL=16 is UNDEFINED
             idx, boff = 0, i
         iregs[RT+idx][60-boff*4:63-boff*4] = result
+```
 
 # Predication Examples
 
 Take the following example:
 
+```
     r10 = 0b00010
     sv.mtcrweird/dm=r10/dz cr8.v, 0, 0b0011.0000
+```
 
 Here, RA is zero, so the source input is zero. The destination is CR Field
 8, and the destination predicate mask indicates to target the first two
@@ -427,6 +447,4 @@ Predicates can be used, on the same sv.mtcrweird instruction.
 
 
 [[!tag standards]]
-----------
 
-\newpage{}

diff --git a/openpower/sv/rfc/ls015.mdwn b/openpower/sv/rfc/ls015.mdwn
index 23c4ad3b770fddf0bed7dc0b93f5f3fadca0616c..1d9029d6baa36d23cd10ec45813fcc1fc30be032 100644 (file)
--- a/openpower/sv/rfc/ls015.mdwn
+++ b/openpower/sv/rfc/ls015.mdwn
@@ -140,9 +140,12 @@ Add `CW2` to the `Formats:` list for `XO (25:31)`.
 
 | Form | Book | Page | Version | Mnemonic | Description |
 |------|------|------|---------|----------|-------------|
-| MM   | I    | #    | 3.2B    | fminmax  | Floating Minimum/Maximum |
-| MM   | I    | #    | 3.2B    | fminmaxs | Floating Minimum/Maximum Single |
-| MM   | I    | #    | 3.2B    | minmax   | Minimum/Maximum |
+| CW2  | I    | #    | 3.2B    | crrweird | |
+| CW2  | I    | #    | 3.2B    | mfcrweird | |
+| CW   | I    | #    | 3.2B    | mtcrrweird | |
+| CW   | I    | #    | 3.2B    | mtcrweird | |
+| CW   | I    | #    | 3.2B    | crweirder | |
+| CW   | I    | #    | 3.2B    | mcrfm | |
 
 [[!tag opf_rfc]]