Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

diff --git a/libreriscv b/libreriscv
index 9a4012b31563923b466ea4889ee8c8847527ff16..c1791bcf40deecca7c60cb7717bdc3fddb9c3061 160000 (submodule)
--- a/libreriscv
+++ b/libreriscv
@@ -1 +1 @@
-Subproject commit 9a4012b31563923b466ea4889ee8c8847527ff16
+Subproject commit c1791bcf40deecca7c60cb7717bdc3fddb9c3061

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 2bf47d5b72a1d4e06d80c995d11bd29488ebdd69..1763bceff514435cfc61ce0e2d9e63ae10596bb2 100644 (file)
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -132,6 +132,17 @@ class ISACaller:
         self.gpr = GPR(decoder2, regfile)
         self.mem = Mem()
         self.pc = PC()
+        # TODO, needed here:
+        # 4.4.4 III p971 SPR (same as GPR except for SPRs - best done as a dict
+        # FPR (same as GPR except for FP nums)
+        # 4.2.2 p124 FPSCR
+        # 2.3.1 CR (and sub-fields CR0..CR6)
+        # 2.3.2 LR   (SPR #8)
+        # 2.3.3 CTR  (SPR #9)
+        # 2.3.4 TAR  (SPR #815)
+        # 3.2.2 p45 XER  (SPR #0)
+        # 3.2.3 p46 p232 VRSAVE (SPR #256)
+
         self.namespace = {'GPR': self.gpr,
                           'MEM': self.mem,
                           'memassign': self.memassign,