sv: allow typenames as function return types

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index ea8cc0765d0e809074259d44e47514825963639c..91b7afddfaa2c7ffe78b2740cc86e2ca469eefb5 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -861,6 +861,7 @@ task_func_decl:
                        outreg->children.push_back($4);
                        outreg->is_signed = $4->is_signed;
                        $4->is_signed = false;
+                       outreg->is_custom_type = $4->type == AST_WIRETYPE;
                }
                current_function_or_task->children.push_back(outreg);
                current_function_or_task_port_id = 1;
@@ -871,6 +872,11 @@ task_func_decl:
        };
 
 func_return_type:
+       hierarchical_type_id {
+               $$ = new AstNode(AST_WIRETYPE);
+               $$->str = *$1;
+               delete $1;
+       } |
        opt_type_vec opt_signedness_default_unsigned {
                $$ = makeRange(0, 0, $2);
        } |

diff --git a/tests/verilog/func_typename_ret.sv b/tests/verilog/func_typename_ret.sv
new file mode 100644 (file)
index 0000000..423975f
--- /dev/null
+++ b/tests/verilog/func_typename_ret.sv
@@ -0,0 +1,35 @@
+typedef logic [1:0] T;
+
+package P;
+    typedef logic [3:0] S;
+endpackage
+
+module gate(
+    output wire [31:0] out1, out2
+);
+    function automatic T func1;
+        input reg signed inp;
+        func1 = inp;
+    endfunction
+    assign out1 = func1(1);
+    function automatic P::S func2;
+        input reg signed inp;
+        func2 = inp;
+    endfunction
+    assign out2 = func2(1);
+endmodule
+
+module gold(
+    output wire [31:0] out1, out2
+);
+    function automatic [1:0] func1;
+        input reg signed inp;
+        func1 = inp;
+    endfunction
+    assign out1 = func1(1);
+    function automatic [3:0] func2;
+        input reg signed inp;
+        func2 = inp;
+    endfunction
+    assign out2 = func2(1);
+endmodule

diff --git a/tests/verilog/func_typename_ret.ys b/tests/verilog/func_typename_ret.ys
new file mode 100644 (file)
index 0000000..7f60499
--- /dev/null
+++ b/tests/verilog/func_typename_ret.ys
@@ -0,0 +1,5 @@
+read_verilog -sv func_typename_ret.sv
+proc
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert