more slides

diff --git a/simple_v_extension/simple_v_chennai_2018.tex b/simple_v_extension/simple_v_chennai_2018.tex
index d2cf1114b728cdd8c7c4429819a6f2c32134f57c..e63c56107b7911807e0352f20b84461458db75b0 100644 (file)
--- a/simple_v_extension/simple_v_chennai_2018.tex
+++ b/simple_v_extension/simple_v_chennai_2018.tex
@@ -182,7 +182,7 @@ for (int i = 0; i < VL; ++i)
    \item SIMD slightly more complex (case above is elwidth = default)  
    \item If s1 and s2 both scalars, Standard branch occurs
    \item Predication stored in integer regfile as a bitfield
-   \item x
+   \item Scalar-vector and vector-vector supported
   \end{itemize}
 \end{frame}
 
@@ -219,6 +219,22 @@ for (int i = 0; i < VL; ++i)
 }
 
 
+\frame{\frametitle{Opcodes, compared to RVV}
+
+ \begin{itemize}
+   \item All integer and FP opcodes removed (no CLIP!)\vspace{10pt}
+   \item VMPOP, VFIRST etc. all removed (use xBitManip)\vspace{10pt}
+   \item VSLIDE removed (just redefine vector)\vspace{10pt}
+   \item VSETVL, VGETVL, VMERGE all stay\vspace{10pt}
+  \end{itemize}
+  Issues:\vspace{10pt}
+  \begin{itemize}
+   \item VCLIP is not in RV*\vspace{10pt}
+   \item Vector copy: use C.MV (MV is a pseudo-op)\vspace{10pt}
+  \end{itemize}
+}
+
+
 \frame{\frametitle{slide}
 
  \begin{itemize}