|ISA <br>name |Num <br>opcodes|Num <br>intrinsics|Taxonomy / <br> Class|setvl <br> scalable|Predicate <br> Masks|Twin <br> Predication|Explicit <br> Vector regs|128-bit <br> ops|Bigint |LDST <br> Fault-First|Data-dependent <br> Fail-first|Predicate-<br> Result|Matrix HW<br> support|
|--------------|---------------|------------------|---------------------|-------------------|--------------------|---------------------|-------------------------|----------------|--------|---------------------|------------------------------|---------------------|---------------------|
|Draft SVP64 |5 (1) |see (25) |Scalable (2) |yes |yes |yes (3) |no (4) |see (5) |yes (6) |yes (7) |yes (8) |yes (9) |yes (10) |
-|VSX |700+ |700+? {26} |Packed SIMD |no |no |no |yes (11) |yes |no |no |no |no |yes (12) |
-|NEON |~250 (13) |7088 {27} |Packed SIMD |no |no |no |yes |yes |no |no |no |no |no |
-|SVE2 |~1000 (14) |6040 {28} |Predicated SIMD(15) |no (15) |yes |no |yes |yes |no |yes (7) |no |no |no |
-|AVX512 (16) |~1000s (17) |7256 (29} |Predicated SIMD |no |yes |no |yes |yes |no |no |no |no |no |
-|RVV (18) |~190 (19) |~25000 {30) |Scalable (20) |yes |yes |no |yes |yes (21) |no |yes |no |no |no |
-|Aurora SX(22) |~200 (23) |unknown {31} |Scalable (24) |yes |yes |no |yes |no |no |no |no |no |no |
+|VSX |700+ |700+? (26) |Packed SIMD |no |no |no |yes (11) |yes |no |no |no |no |yes (12) |
+|NEON |~250 (13) |7088 (27) |Packed SIMD |no |no |no |yes |yes |no |no |no |no |no |
+|SVE2 |~1000 (14) |6040 (28) |Predicated SIMD(15) |no (15) |yes |no |yes |yes |no |yes (7) |no |no |no |
+|AVX512 (16) |~1000s (17) |7256 (29) |Predicated SIMD |no |yes |no |yes |yes |no |no |no |no |no |
+|RVV (18) |~190 (19) |~25000 (30) |Scalable (20) |yes |yes |no |yes |yes (21) |no |yes |no |no |no |
+|Aurora SX(22) |~200 (23) |unknown (31) |Scalable (24) |yes |yes |no |yes |no |no |no |no |no |no |
* (1): plus EXT001 24-bit prefixing. See [[sv/svp64]]
* (2): A 2-Dimensional Scalable Vector ISA **specifically designed for the Power ISA** with both Horizontal-First and Vertical-First Modes. See [[sv/vector_isa_comparison]]
* (24): Like the original Cray Vectors, the ISA Vector Length is independent of the underlying hardware, however Generation 1 has 256 elements per Vector register (3.2.4 p24, Aurora ISA guide)
* (25): If treated as a 1-Dimensional ISA, the 24-bit Prefix expands 200+ scalar instructions to well over a million intrinsics (N **times** M).
If treated as a 2-Dimensional ISA there are far less. N prefix intrinsics **plus** M scalar instruction intrinsics, where N is of the order of 10^4 and M is of the order of 10^2.
-* {26}: [https://gcc.gnu.org/onlinedocs/gcc/PowerPC-AltiVec_002fVSX-Built-in-Functions.html](Altivec gcc intrinsic), contains links to additional VSX intrinsics for ISA 2.05/6/7, 3.0 and 3.1
+* (26): [https://gcc.gnu.org/onlinedocs/gcc/PowerPC-AltiVec_002fVSX-Built-in-Functions.html](Altivec gcc intrinsic), contains links to additional VSX intrinsics for ISA 2.05/6/7, 3.0 and 3.1
* (27): NEON 32-bit 2754 intrinsics, NEON 64-bit 4334 intrinsics.
* (28): SVE: 4140 intrinsics, SVE2 1900 intrinsics
* (29): Count includes SSE, SSE2, AVX, AVX2 and all AVX512 variants
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