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@@ -4,6 +4,8 @@ This page aims to collect all the resources and specifications we need
 in one place for quick access. We will try our best to keep links here
 up-to-date. Feel free to add more links here.
 
+[[!toc  ]]
+
 # OpenPOWER ISA
 
 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
@@ -11,8 +13,11 @@ up-to-date. Feel free to add more links here.
 
 # RISC-V Instruction Set Architecture
 
+**PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
+RISCV
+
 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
-of the project implies, we will be following the RISC-V ISA due to it
+of the project implies, we will be following the RISC-V ISA I due to it
 being open-source and also because of the huge software and hardware
 ecosystem building around it. There are other open-source ISAs but none
 of them have the same momentum and energy behind it as RISC-V.
@@ -92,6 +97,19 @@ although performance is not evaluated.
 
 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
 
+# Various POWER Communities
+ - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
+   I still can't figure out if this chip is POWER8 or POWER9. Please verify!
+ - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/]
+   Supporting/Raising awareness of various POWER related open projects on the FOSS
+   community
+ - [OpenPOWER](https://openpowerfoundation.org)
+   Promotes and ensure compliance with the Power ISA amongst members.
+ - [OpenCapi](https://opencapi.org)
+   High performance interconnect for POWER machines. One of the big advantages
+   of the POWER architecture. Notably more performant than PCIE Gen4, and is
+   designed to be layered on top of the physical PCIE link.
+
 # Free Silicon Conference
 
 The conference brought together experts and enthusiasts who want to build