Create personal page.

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+# Samuel A. Falvo II
+
+Individual Contributor.
+
+# Status tracking
+
+Move things along from one stage to the next.
+
+## Currently working on
+
+ - [https://bugs.libre-soc.org/show_bug.cgi?id=418](SPR pipeline formal correctness proof needed)
+
+## Completed but not yet submitted:
+
+## Submitted for NLNet RFP
+
+Submitted but not confirmed paid:
+
+## Paid
+
+Donation from NLNet confirmed received:
+

diff --git a/about_us.mdwn b/about_us.mdwn
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@@ -120,15 +120,15 @@ Alain's website: <http://phcomp.co.uk>
 * LinkedIn Profile: [[https://www.linkedin.com/in/sanjay-menon-91791815a]]
 * Availability: ~6hrs/week
 
-## Samuel Falvo
+## [[Samuel A Falvo II]]
 
 * Experience in amateur HDL projects (Kestrel-3 homebrew computer
    concept; VDC-II core), Verilog (but not System Verilog), newbie at PCB
-   design.  Extensive experience with test-driven development, Python, RISC-V
-   assembly language, and Forth.  Very comfortable with nMigen, but still
-   learning things.
+   design.  Extensive experience with test-driven development, Python,
+   assembly language for a wide variety of CPUs including RISC-V, and Forth.
+   Very comfortable with nMigen, but still learning things.
 * Interests: Forth, Common Lisp, Scheme, assembly language,
-   {Astro|Semiconductor-}physics, astronomy, martial arts, furry
+   {Astro|Semiconductor-}physics, astronomy, martial arts, furry (character: black dragon; name: "Vertigo").
 * Websites:
   - https://hackaday.io/project/170581-vdc-ii ,
   - https://kestrelcomputer.github.io/kestrel/ ,