class IO(object):
def __init__(self, typ, name):
self.typ = typ
+ self.name = name
if typ == 'in' or typ == 'inout':
self.inp = Signal(bool(0))
if typ == 'out' or typ == 'inout':
return Foo(test2)
-def create_test():
+def create_test(npins=2, nfns=4):
x = """\
-def getfn({0}):
- def test({0}):
- args = ({0})
- return test2(*args)
- return test
+from myhdl import block
+@block
+def test(testfn, clk, num_pins, num_fns, {0}):
+ args = [{0}]
+ return testfn(clk, num_pins, num_fns, args)
"""
- args = ['clk', 'muxes', 'pins', 'fns']
+
+ args = []
+ for pnum in range(npins):
+ args.append("sel%d" % pnum)
+ args.append("pin%d" % pnum)
+ for pnum in range(nfns):
+ args.append("fn%d" % pnum)
args = ','.join(args)
x = x.format(args)
print x
print repr(x)
- y = {'test2': test2, 'block': block}
+ with open("testmod.py", "w") as f:
+ f.write(x)
+ x = "from testmod import test"
code = compile(x, '<string>', 'exec')
+ y = {}
exec code in y
- x = y["getfn"]
- #print inspect.getsourcelines(proxy)
- #print inspect.getsourcelines(x)
+ x = y["test"]
def fn(*args):
return block(x)
return wrapper
-def test2(clk, muxes, pins, fns):
+@block
+def test2(clk, num_pins, num_fns, args):
+ muxes = []
+ pins = []
+ fns = []
+ for i in range(num_pins):
+ muxes.append(args.pop(0))
+ pins.append(args.pop(0))
+ for i in range(num_fns):
+ fns.append(args.pop(0))
muxinst = []
pins = []
ins = []
outs = []
+ dirs = []
+ fins = []
+ fouts = []
+ fdirs = []
+ args = []
for i in range(2):
m = Mux()
muxes.append(m)
muxvals.append(m.sel)
+ args.append(m)
pin = IO("inout", "name%d" % i)
pins.append(pin)
+ args.append(pin)
ins.append(pin.inp)
outs.append(pin.out)
+ dirs.append(pin.dirn)
fns = []
for i in range(4):
- fns.append(IO("inout", "fnname%d" % i))
+ fn = IO("inout", "fnname%d" % i)
+ fns.append(fn)
+ fins.append(fn.inp)
+ fouts.append(fn.out)
+ fdirs.append(fn.dirn)
+ args.append(fn)
clk = Signal(bool(0))
- mux_inst = Test(clk, muxes, pins, fns)
+ mux_inst = test(test2, clk, 2, 4, *args)
@instance
def clk_signal():
pins = []
ins = []
outs = []
-
+ dirs = []
+ fins = []
+ fouts = []
+ fdirs = []
+ args = []
for i in range(2):
m = Mux()
muxes.append(m)
muxvals.append(m.sel)
+ args.append(m)
pin = IO("inout", "name%d" % i)
pins.append(pin)
+ args.append(pin)
ins.append(pin.inp)
outs.append(pin.out)
+ dirs.append(pin.dirn)
fns = []
for i in range(4):
- fns.append(IO("inout", "fnname%d" % i))
+ fn = IO("inout", "fnname%d" % i)
+ fns.append(fn)
+ fins.append(fn.inp)
+ fouts.append(fn.out)
+ fdirs.append(fn.dirn)
+ args.append(fn)
clk = Signal(bool(0))
- mux_inst = Test(clk, muxes, pins, fns)
+ mux_inst = test(test2, clk, 2, 4, *args)
+ mux_inst.convert(hdl="Verilog", initial_values=True)
+ #mux_inst = Test(clk, muxes, pins, fns)
#toVerilog(mux_inst, clk, muxes, pins, fns)
#deco = Deco()
#b = _Block(mux_inst, deco, "test", "test.py", 1, clk, muxes, pins, fns)
tb.config_sim(trace=True)
tb.run_sim(66 * period) # run for 15 clock cycle
-#test = create_test()
+test = create_test()
if __name__ == '__main__':
# ok now set up gpioa0, set it to the opposite of twi_sda (0) i.e. gpioa0=1
# and test that... then switch over pin0/mux=3
- dut.peripheral_side_gpioa_a0_outen_in = 0 # settings for input
+ dut.peripheral_side_gpioa_a0_outen_in = 0 # settings for input
dut.mux_lines_cell0_mux_in = 0
dut.EN_mux_lines_cell0_mux = 1
dut.iocell_side_io0_cell_in_in = 1 # twi_sda=0, so gpioa0 should be 1
dut._log.info("Ok!, twi_sda test2 passed")
+
@cocotb.test()
def pinmux_twi_sda3(dut):
"""Test for I2C multi-pin one FN_out (route 2 pins out to same function)
dut.EN_mux_lines_cell2_mux = 0
# first check the working of twi_sda at cell1
-
+
# TWI
yield Timer(2)
# define input variables
dut.peripheral_side_twi_sda_outen_in = 1
yield Timer(2)
- # the output passed by twi_sda = 0 should be passed
+ # the output passed by twi_sda = 0 should be passed
# to io1_cell__out
dut._log.info("io1_out %s" % dut.iocell_side_io1_cell_out)
# Test for out for twi_sda
raise TestFailure(
"twi_sda=0/mux=2/out=1 %s iocell_io1 != 0" %
str(dut.iocell_side_io1_cell_out))
-
+
dut.peripheral_side_twi_sda_out_in = 1
yield Timer(2)
# ok, now io1_cell_out should be equal to 1
dut.mux_lines_cell0_mux_in = 3
dut.EN_mux_lines_cell0_mux = 1
yield Timer(2)
- # ok, now the output io0_cell_out should be 1 as
+ # ok, now the output io0_cell_out should be 1 as
# FNout remains is not changed
# this also tests the working of twi_sda at cell0
# Now, let's test the working of output muxing logic
# at cell 0, by enabling the mux selection line for
- # gpio 0. The io0_cell_out should change, but
+ # gpio 0. The io0_cell_out should change, but
# twi_sda should remain at value 1
# so set value of gpio0_out_in = 0
"twi_sda=0/mux=0/out=1 %s iocell_io0 != 0" %
str(dut.iocell_side_io2_cell_out))
- # Now, let's test the working of output muxing logic
- # at cell1. First, the output of io1_cell_out should
- # be the previous value (1).
+ # Now, let's test the working of output muxing logic
+ # at cell1. First, the output of io1_cell_out should
+ # be the previous value (1).
yield Timer(2)
if dut.iocell_side_io1_cell_out != 1:
raise TestFailure(
"twi_sda=1/mux=2/out=1 %s iocell_io1 != 1" %
str(dut.iocell_side_io1_cell_out))
-
+
# ok, now set the muxing selection line for gpio1
# again, the value of gpio_out_in should be 0
# ie. opposite of twi_sda_out
projects / pinmux.git / commitdiff