reduce instruction depth to 6 bits in TestIssuer

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 66f1245e93db3591bbdfcb8a2ee7ba106f4fa847..0b6ea0cb6ec86e188be9c7a5a45257ae66399d17 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -315,7 +315,7 @@ class TestIssuer(Elaboratable):
 
     efficiency and speed is not the main goal here: functional correctness is.
     """
-    def __init__(self, addrwid=6, idepth=16):
+    def __init__(self, addrwid=6, idepth=6):
         # main instruction core
         self.core = core = NonProductionCore(addrwid)
 

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 7e13dfe8ec97e02e03ea310c8168550b6a9afafa..3382cce49e34d0caf5605b4f5753b8dcf19fa527 100644 (file)
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -33,7 +33,6 @@ from soc.fu.ldst.test.test_pipe_caller import LDSTTestCase
 
 def setup_regs(core, test):
 
-
     # set up INT regfile, "direct" write (bypass rd/write ports)
     intregs = core.regs.int
     for i in range(32):
@@ -71,6 +70,7 @@ def setup_regs(core, test):
         yield xregs.regs[xregs.CA].reg.eq(0)
 
     # XER
+    pdecode2 = core.pdecode2
     so = yield xregs.regs[xregs.SO].reg
     ov = yield xregs.regs[xregs.OV].reg
     ca = yield xregs.regs[xregs.CA].reg