relative imports

diff --git a/src/ieee754/add/test_fsm_experiment.py b/src/ieee754/add/test_fsm_experiment.py
index cfc401e8de025ed5b073b1d11c976e39c530e553..eeff6f0aae714be8b2f125b41f69bcab1608e442 100644 (file)
--- a/src/ieee754/add/test_fsm_experiment.py
+++ b/src/ieee754/add/test_fsm_experiment.py
@@ -10,7 +10,7 @@ from ieee754.fpcommon.fpbase import (FPNumIn, FPNumOut, FPOpIn,
                                      FPOpOut, FPBase)
 from nmutil.nmoperator import eq
 from nmutil.singlepipe import SimpleHandshake, ControlBase
-from test_buf_pipe import data_chain2, Test5
+from nmutil.test.test_buf_pipe import data_chain2, Test5
 
 
 class FPDIV(FPBase, Elaboratable):

diff --git a/src/nmutil/test/test_buf_pipe.py b/src/nmutil/test/test_buf_pipe.py
index 089163c5f061e4dddf4510beff7b1e5a9648997a..f9a4e50d3491cc87a81d5fd6ca5494a2e802f480 100644 (file)
--- a/src/nmutil/test/test_buf_pipe.py
+++ b/src/nmutil/test/test_buf_pipe.py
@@ -19,11 +19,11 @@ from nmigen.hdl.rec import Record
 from nmigen.compat.sim import run_simulation
 from nmigen.cli import verilog, rtlil
 
-from example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
-from example_buf_pipe import ExamplePipeline, UnbufferedPipeline
-from example_buf_pipe import ExampleStageCls
-from example_buf_pipe import PrevControl, NextControl, BufferedHandshake
-from example_buf_pipe import StageChain, ControlBase, StageCls
+from .example_buf_pipe import ExampleBufPipe, ExampleBufPipeAdd
+from .example_buf_pipe import ExamplePipeline, UnbufferedPipeline
+from .example_buf_pipe import ExampleStageCls
+from .example_buf_pipe import PrevControl, NextControl, BufferedHandshake
+from .example_buf_pipe import StageChain, ControlBase, StageCls
 from nmutil.singlepipe import UnbufferedPipeline2
 from nmutil.singlepipe import SimpleHandshake
 from nmutil.singlepipe import PassThroughHandshake