add option to enable/disable bus forwarding mode on INT regfile

diff --git a/src/soc/regfile/regfile.py b/src/soc/regfile/regfile.py
index 30063726137032501e6838f5712d690395d91de6..710fc268d7e578e4cd3fbdb7731c5c4dc61aa515 100644 (file)
--- a/src/soc/regfile/regfile.py
+++ b/src/soc/regfile/regfile.py
@@ -107,11 +107,12 @@ class RegFileArray(Elaboratable):
         and read-en signals (per port).
     """
 
-    def __init__(self, width, depth, synced=True):
+    def __init__(self, width, depth, synced=True, fwd_bus_mode=True):
         self.synced = synced
         self.width = width
         self.depth = depth
-        self.regs = Array(Register(width, synced=synced) \
+        self.regs = Array(Register(width, synced=synced,
+                                   writethru=fwd_bus_mode) \
                           for _ in range(self.depth))
         self._rdports = []
         self._wrports = []

diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index 030a8d28c0b136f2ef46220444ec11841ffffc1d..8ac0b123f07968cb0c6b210b8e74521ef7a33d77 100644 (file)
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -70,7 +70,7 @@ class IntRegs(RegFileMem): #class IntRegs(RegFileArray):
     * write-through capability (read on same cycle as write)
     """
     def __init__(self, svp64_en=False, regreduce_en=False):
-        super().__init__(64, 32)
+        super().__init__(64, 32, fwd_bus_mode=not regreduce_en)
         self.w_ports = {'o': self.write_port("dest1"),
                         }
         self.r_ports = {