bit of a mess, got a working check against static ExpectedState

needed to extract state from the simulator *inside* the nmigen process()
function

diff --git a/src/openpower/decoder/isa/test_caller_shift_rot.py b/src/openpower/decoder/isa/test_caller_shift_rot.py
index 06460feb53b59448c4ce631cf465a036498f95f6..d8fa5eb043f2afb65f8f0fce9b121018f19c9450 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_shift_rot.py
+++ b/src/openpower/decoder/isa/test_caller_shift_rot.py
@@ -5,6 +5,7 @@ from openpower.test.state import ExpectedState, TestState
 from openpower.simulator.program import Program
 from openpower.decoder.selectable_int import SelectableInt
 from openpower.decoder.isa.test_runner import run_tst
+from openpower.test.state import TestState
 
 
 class DecoderTestCase(FHDLTestCase):
@@ -21,8 +22,7 @@ class DecoderTestCase(FHDLTestCase):
         e.intregs[3] = 0x8800
         with Program(lst, bigendian=False) as program:
             # and here lies the rabbit hole...at least for me
-            sim = self.run_tst_program(program, initial_regs)
-            yield from self.check_regs(sim, e)
+            sim = self.run_tst_program(program, initial_regs, expected=e)
     """
     def test_case_srw_1(self):
         lst = ["sraw 3, 1, 2"]
@@ -207,16 +207,23 @@ class DecoderTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(3), SelectableInt(0xffffffff80122900, 64))
     """
 
-    def run_tst_program(self, prog, initial_regs=[0] * 32, initial_mem=None):
-        simulator = run_tst(prog, initial_regs, mem=initial_mem)
+    def run_tst_program(self, prog, initial_regs=[0] * 32, initial_mem=None,
+                                    expected=None):
+        simulator = run_tst(prog, initial_regs, mem=initial_mem,
+                                   state=(self, 0))
+
         simulator.gpr.dump()
+        # this is by no means perfect... needs work but it's functional
+        if expected is not None:
+            # have to put these in manually
+            expected.to_test = expected
+            expected.dut = self
+            expected.state_type = "expected"
+            expected.code = 0
+            # do actual comparison
+            simulator.state.compare(expected)
         return simulator
 
-
-    def check_regs(self, sim, e):
-        simstate = yield from TestState("sim",sim,self)
-        yield from simstate.compare(e)
-
     """
     def check_regs(self, sim, e):
         # int regs

diff --git a/src/openpower/decoder/isa/test_runner.py b/src/openpower/decoder/isa/test_runner.py
index eac1295457c916894eb3a300fded0ffe372f8385..b49ec6ff781aea3c39dc82ae8207e64b76d09f58 100644 (file)
--- a/src/openpower/decoder/isa/test_runner.py
+++ b/src/openpower/decoder/isa/test_runner.py
@@ -6,6 +6,7 @@ from openpower.decoder.power_decoder2 import (PowerDecode2)
 from openpower.simulator.program import Program
 from openpower.decoder.isa.caller import ISACaller, inject
 from openpower.decoder.isa.all import ISA
+from openpower.test.state import TestState
 from nmutil.formaltest import FHDLTestCase
 
 
@@ -87,10 +88,17 @@ class ISATestRunner(FHDLTestCase):
             sim.run()
 
 
+def check_regs(dut, sim, expected, test, code):
+    # create the two states and compare
+    testdic = {'sim': sim, 'expected': expected}
+    yield from teststate_check_regs(dut, testdic, test, code)
+
+
 def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
                                      initial_cr=0, mem=None,
                                      initial_fprs=None,
-                                     pdecode2=None):
+                                     pdecode2=None,
+                                     state=None): # (dut, code)
     if initial_sprs is None:
         initial_sprs = {}
     m = Module()
@@ -117,6 +125,8 @@ def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
     comb += pdecode2.dec.raw_opcode_in.eq(instruction)
     sim = Simulator(m)
 
+    process_state = state
+
     def process():
 
         print ("GPRs")
@@ -145,10 +155,16 @@ def run_tst(generator, initial_regs, initial_sprs=None, svstate=0, mmu=False,
             pc = simulator.pc.CIA.value
             index = pc//4
 
+        # use this to test against expected (static) results at end of run
+        if process_state is not None:
+            (dut, code) = process_state
+            simulator.state = yield from TestState("sim", simulator, dut, code)
+
     sim.add_process(process)
     with sim.write_vcd("simulator.vcd", "simulator.gtkw",
                        traces=[]):
         sim.run()
+
     return simulator