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diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 42bf34158f2d0ef89f3995732d183be46de7fda6..7b7dce40ec980ec2f38563a06701da3a00d43f87 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -61,13 +61,15 @@ which is a different convention from that used elsewhere in the Power ISA.
 The SVP64 prefix always comes before the suffix in PC order and must be
 considered an independent "Defined word" that augments the behaviour of
 the following instruction, but does **not** change the actual Decoding
-of that following instruction.  **All prefixed instructions retain their
-non-prefixed encoding and definition**.
+of that following instruction.  **All prefixed 32-bit instructions
+(Defined Words) retain their non-prefixed encoding and definition**.
 
 Two apparent exceptions to the above hard rule exist: SV Branch-Conditional
 operations and LD/ST-update "Post-Increment" Mode.  Post-Increment
 was considered sufficiently high priority (significantly reducing hot-loop
-instruction count) that one bit in the Prefix is reserved for it.
+instruction count) that one bit in the Prefix is reserved for it
+(Note the intention to release that bit and move Post-Increment instructions
+to EXT2xx).
 Vectorised Branch-Conditional operations "embed" the original Scalar
 Branch-Conditional behaviour into a much more advanced variant that
 is highly suited to High-Performance Computation (HPC), Supercomputing,