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diff --git a/3d_gpu/architecture.mdwn b/3d_gpu/architecture.mdwn
index a201b8677e5aa448928234b158f14785a21620bb..3087258467ca2bea0b11df201b64d3420fa5cd59 100644 (file)
--- a/3d_gpu/architecture.mdwn
+++ b/3d_gpu/architecture.mdwn
@@ -32,6 +32,10 @@ This means that in low clock rate modes the length of the whole pipeline may be
 
 The only reason why this ingenious and elegant trick (deployed first by IBM in the 1990s) can be considered is down to the fact that the 6600 Style Dependency Matrices do not care about actual completion time, they only care about availability of the result.
 
+# Decoder
+
+TODO, see [[architecture/decoder]]
+
 # Memory and Cache arrangement
 
 Section TODO, with own page [[architecture/memory_and_cache]]  LD/ST accesses are controlled by the 6600-style Dependency Matrices