(no commit message)

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index ec1d7e053d221ee680a69eed6bd11dbd7c1015b8..5df9ca336416fe92052816424678517cabc51dd6 100644 (file)
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -721,15 +721,15 @@ use which remaps is here [[opcode_regs_deduped]].
 **Please note the following**:
 
 ```
-    Machine-readable CSV files have been provided which will make the task
-    of creating SV-aware ISA decoders, documentation, assembler tools
+    Machine-readable CSV files have been autogenerated which will make the
+    task of creating SV-aware ISA decoders, documentation, assembler tools
     compiler tools Simulators documentation all aspects of SVP64 easier
     and less prone to mistakes.  Please avoid manual re-creation of
-    information from the written specification wording, and use the
-    CSV files or use the Canonical tool which creates the CSV files,
-    named sv_analysis.py. The information contained within sv_analysis.py
-    is considered to be part of this Specification, even encoded as it
-    is in python3.
+    information from the written specification wording in this chapter,
+    and use the CSV files or use the Canonical tool which creates the CSV
+    files, named sv_analysis.py. The information contained within
+    sv_analysis.py is considered to be part of this Specification, even
+    encoded as it is in python3.
 ```
 
 The mappings are part of the SVP64 Specification in exactly the same