test/test_packet: add randomness on ready output, fix corner-cases on Packetizer...

diff --git a/litex/soc/interconnect/packet.py b/litex/soc/interconnect/packet.py
index eee4e833263434fec4c6554809116592adfc1743..e60ce53bac045e662dfc79aeb9ae810c8d9a28b7 100644 (file)
--- a/litex/soc/interconnect/packet.py
+++ b/litex/soc/interconnect/packet.py
@@ -238,7 +238,7 @@ class Packetizer(Module):
             )
         )
         header_offset_multiplier = 1 if header_words == 1 else 2
-        self.sync += If(sink.ready, sink_d.eq(sink))
+        self.sync += If(source.ready, sink_d.eq(sink))
         fsm.act("UNALIGNED-DATA-COPY",
             source.valid.eq(sink.valid | sink_d.last),
             source.last.eq(sink_d.last),
@@ -249,7 +249,7 @@ class Packetizer(Module):
             ),
             source.data[header_leftover*8:].eq(sink.data),
             If(source.valid & source.ready,
-                sink.ready.eq(1),
+                sink.ready.eq(~source.last),
                 NextValue(fsm_from_idle, 0),
                 If(source.last,
                     NextState("IDLE")
@@ -339,11 +339,11 @@ class Depacketizer(Module):
                 )
             )
         )
-        self.sync += If(sink.valid & sink.ready, sink_d.eq(sink))
+        self.sync += If(sink.ready, sink_d.eq(sink))
         fsm.act("UNALIGNED-DATA-COPY",
             source.valid.eq((sink.valid & ~fsm_from_idle) | no_payload),
             source.last.eq(sink.last | no_payload),
-            sink.ready.eq(source.ready),
+            sink.ready.eq(source.ready | fsm_from_idle),
             If(sink.valid & sink.ready,
                 NextValue(fsm_from_idle, 0),
                 If(fsm_from_idle,

diff --git a/test/test_packet.py b/test/test_packet.py
index 26a8aefba8302f058a812ae5c727f59f5388aa0f..b7e7a3343f527760e8a1b146b65ce9f6d46db70f 100644 (file)
--- a/test/test_packet.py
+++ b/test/test_packet.py
@@ -74,16 +74,21 @@ class TestPacket(unittest.TestCase):
                     while prng.randrange(100) < valid_rand:
                         yield
 
-        def checker(dut):
+        def checker(dut, ready_rand=50):
             dut.header_errors = 0
             dut.data_errors   = 0
             dut.last_errors   = 0
             # Receive and check packets
-            yield dut.source.ready.eq(1)
             for packet in packets:
                 for n, data in enumerate(packet.datas):
+                    yield dut.source.ready.eq(0)
+                    yield
                     while (yield dut.source.valid) == 0:
                         yield
+                    while prng.randrange(100) < ready_rand:
+                        yield
+                    yield dut.source.ready.eq(1)
+                    yield
                     for field in ["field_8b", "field_16b", "field_32b", "field_64b", "field_128b"]:
                         if (yield getattr(dut.source, field)) != packet.header[field]:
                             dut.header_errors += 1
@@ -92,7 +97,6 @@ class TestPacket(unittest.TestCase):
                         dut.data_errors += 1
                     if ((yield dut.source.last) != (n == (len(packet.datas) - 1))):
                         dut.last_errors += 1
-                    yield
             yield
 
         class DUT(Module):