add DDR link

diff --git a/shakti/m_class.mdwn b/shakti/m_class.mdwn
index 6dc5420d4e7ac986ed7868edb4da1bfa864141a2..9f96863e49c9a176feb060186fd45884a4ff8dee 100644 (file)
--- a/shakti/m_class.mdwn
+++ b/shakti/m_class.mdwn
@@ -217,7 +217,7 @@ TBD
 * 32x [[EINT]]-cable GPIO with full edge-triggered and low/high IRQ capability
 * 1x [[I2S]] audio with 4-wire output and 1-wire input.
 * 3x USB2 (ULPI for reduced pincount) each capable of USB-OTG support
-* DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
+* [[DDR]] DDR3/DDR3L/LPDDR3 32-bit-wide memory controller
 * [[JTAG]] for debugging
 
 Some interfaces at:
@@ -235,6 +235,7 @@ Some interfaces at:
 List of Interfaces:
 
 * [[CSI]]
+* [[DDR]]
 * [[JTAG]]
 * [[I2C]]
 * [[I2S]]