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diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 3cced7dd8002414c4b626606ff6b07efa70b99a9..71e9925ba606d04aeed8197921c2a5219ed6a2d2 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -135,6 +135,14 @@ Due to the need for exceptions to occur in the middle, the loop should *not* be
 * TestIssuer: part done <https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=92ba64ea13794dea71816be746a056d52e245651>
 * Microwatt: TODO
 
+Remember the following register files need to have for-loops, plus
+unit tests:
+
+* GPR
+* SPRs (yes, really: mtspr and mfspr are SV Context-extensible)
+* Condition Registers
+* FPR (if present)
+
 ## Increasing register file sizes
 
 TODO.  INTs, FPs, CRs, these all increase to 128.  Welcome To Vector ISAs.