whoops, off-by-one in use of mw, in multiply_1 stage

diff --git a/src/add/fmul.py b/src/add/fmul.py
index bb508e1a4733b61427c688d3d9488dee9c5f490c..d7466fc369372f0411204ccd0319941c8a25c3b5 100644 (file)
--- a/src/add/fmul.py
+++ b/src/add/fmul.py
@@ -106,9 +106,9 @@ class FPMUL(FPBase):
                 mw = z.m_width
                 m.next = "normalise_1"
                 m.d.sync += [
-                z.m.eq(product[mw+3:]),
-                of.guard.eq(product[mw+2]),
-                of.round_bit.eq(product[mw+1]),
+                z.m.eq(product[mw+2:]),
+                of.guard.eq(product[mw+1]),
+                of.round_bit.eq(product[mw]),
                 of.sticky.eq(product[0:mw] != 0)
             ]