(no commit message)

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index cf2e618bfc0c1921746635de561cf07425d7b623..b694ee4f39a5d82b0e71c4030fd9d383f768f0db 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -526,7 +526,8 @@ in Multi-Issue Micro-architectures.
 
 If combined with Vertical-First then much more complex operations may exploit
 REMAP Schedules, such as Complex Number FFTs, by using Scalar intermediary
-temporary registers to compute results that have a Vector destination.
+temporary registers to compute results that have a Vector source
+or destination or both.
 Contrast this with a Standard Horizontal-First Vector ISA where the only
 way to perform Vectorised Complex Arithmetic would be to add Complex Vector
 Arithmetic operations.