increase wishbone address width to 29 for xics and gpio

this may not be exactly correct, have to see how it goes

diff --git a/src/soc/litex/florent/libresoc/core.py b/src/soc/litex/florent/libresoc/core.py
index d28d424d6fb4a9230854217bc5e4562ac536b1b8..23a363b92b4e4d39aee93f09758de4406f9d6a48 100644 (file)
--- a/src/soc/litex/florent/libresoc/core.py
+++ b/src/soc/litex/florent/libresoc/core.py
@@ -61,9 +61,9 @@ class LibreSoC(CPU):
             self.data_width           = 64
         self.ibus = ibus = wishbone.Interface(data_width=64, adr_width=29)
 
-        self.xics_icp = icp = wishbone.Interface(data_width=32, adr_width=5)
-        self.xics_ics = ics = wishbone.Interface(data_width=32, adr_width=14)
-        self.simple_gpio = gpio = wishbone.Interface(data_width=32, adr_width=5)
+        self.xics_icp = icp = wishbone.Interface(data_width=32, adr_width=29)
+        self.xics_ics = ics = wishbone.Interface(data_width=32, adr_width=29)
+        self.simple_gpio = gpio = wishbone.Interface(data_width=32, adr_width=29)
 
         self.periph_buses = [ibus, dbus]
         self.memory_buses = []