(no commit message)

diff --git a/nlnet_2021_lip6_vlsi.mdwn b/nlnet_2021_lip6_vlsi.mdwn
index 05ee74591e9288bbea4d22b2983419d5ed73e7ef..200374f0b04518b81243d6b762c311641c12cf63 100644 (file)
--- a/nlnet_2021_lip6_vlsi.mdwn
+++ b/nlnet_2021_lip6_vlsi.mdwn
@@ -26,7 +26,7 @@ engendered and fostered where at present NDAs rife through the VLSI
 Industry prevent and prohibit discussion and general improvements beneficial
 to users.
 
-The expected outcome is to improve Coriolis2, HITAS/TAGLE and extend the
+The expected outcome is to improve Coriolis2, HITAS/YAGLE and extend the
 whole toolchain so that it is faster, able to handle larger ASIC designs,
 and can perform Logical Validation. Also to be improved and tested is
 support for lower geometries (starting with 130nm)
@@ -47,7 +47,7 @@ EUR $50,000.
 To improve the speed of the GUI front-end, to make it possible to
 handle larger ASIC designs, to add LVS capability, improve the internal
 data format (to better handle mixed case module and signal names), integrate
-the Static Timing Analysis tool (HITAS, TAGLE), to complete the conversion
+the Static Timing Analysis tool (HITAS) and YAGLE gate-level extraction tool, to complete the conversion
 to python 3,
 to try smaller geometry ASICs (beginning with 130nm), and potentially
 investigate using multi-processing to speed up completion.