field number ordering wrong way round?

see https://bugs.libre-soc.org/show_bug.cgi?id=325#c107

diff --git a/src/soc/fu/trap/formal/proof_main_stage.py b/src/soc/fu/trap/formal/proof_main_stage.py
index 511ad9cb0962b90a82be7fec46411decacdb2924..6f24bd194c20e5fd5e52a5fbf4a90a37ebb029d3 100644 (file)
--- a/src/soc/fu/trap/formal/proof_main_stage.py
+++ b/src/soc/fu/trap/formal/proof_main_stage.py
@@ -182,10 +182,15 @@ class Driver(Elaboratable):
                 comb += expected_msr[MSR.PR].eq(0)
                 comb += expected_msr[MSR.FP].eq(0)
                 comb += expected_msr[MSR.PMM].eq(0)
+                # TODO: check ordering (which is smaller, which is larger)
+                # MSR.TSs or MSR.TSe+1?
                 comb += expected_msr[MSR.TEs:MSR.TEe+1].eq(0)
                 comb += expected_msr[MSR.UND].eq(0)
                 comb += expected_msr[MSR.LE].eq(1)
 
+                # TODO: check ordering (which is smaller, which is larger)
+                # MSR.TSs or MSR.TSe+1?
+                # see https://bugs.libre-soc.org/show_bug.cgi?id=325#c107
                 with m.If(op.msr[MSR.TSs:MSR.TSe+1] == 0b10):
                     comb += expected_msr[MSR.TSs:MSR.TSe+1].eq(0b01)
                 with m.Else():

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 548e0cfb3c21fc61b2944e18e2814419018c7113..e41ccce18316bbe38970776c4c74dc848753f471 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -103,6 +103,8 @@ class TrapMainStage(PipeModBase):
         comb += msr_o.data[MSR.VEC].eq(0)
         comb += msr_o.data[MSR.FP].eq(0)
         comb += msr_o.data[MSR.PMM].eq(0)
+        # XXX check ordering
+        # see https://bugs.libre-soc.org/show_bug.cgi?id=325#c107
         comb += msr_o.data[MSR.TEs:MSR.TEe+1].eq(0)
         comb += msr_o.data[MSR.UND].eq(0)
         if msr_hv is not None: