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ruby: Fix MESI consistency bug
authorMarco Elver <marco.elver@ed.ac.uk>
Sun, 7 Jun 2015 19:02:40 +0000 (14:02 -0500)
committerMarco Elver <marco.elver@ed.ac.uk>
Sun, 7 Jun 2015 19:02:40 +0000 (14:02 -0500)
Fixes missed forward eviction to CPU. With the O3CPU this can lead to load-load
reordering, as the LQ is never notified of the invalidate.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>

src/mem/protocol/MESI_Two_Level-L1cache.sm patch | blob | history

diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
index b449c4f2b03b2ae355213fa954d830cf7c9ea4b8..4f9928bf156b012be7e15d7549e60761f54eb346 100644 (file)
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -1341,6 +1341,7 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
 
   // transitions from SM
   transition(SM, Inv, IM) {
+    forward_eviction_to_cpu;
     fi_sendInvAck;
     dg_invalidate_sc;
     l_popRequestQueue;